1. Field of the Invention
The present invention relates to a nonvolatile memory device, and in particular, to an advanced NOR-type mask ROM (read-only memory) and a fabricating method thereof.
2. Description of the Related Art
To satisfy the demands for high integration, low cost, and high-speed operation, mask ROM cell structures have recently shifted from a NAND type to a NOR type. A conventional NOR-type cell is operated at high speed with a high cell current but with an increased cell area. In contrast, a conventional NAND-type cell occupies a small cell area and thus can be packed on a chip with high density, but has a low cell current.
NOR flat cells are those that have recently been developed to be free of a field oxide film for isolating devices and made as small as a NAND-type cell, while still having the advantages of a NOR-type cell. Such a NOR flat cell offers the benefits of high speed and low voltage operation with a relatively high cell current and excellent cell uniformity. Such a NOR flat cell also facilitates application of a multi-bit or multi-level memory for storing several items of data in one cell. For an example of a flat cell array and a fabricating method thereof, see U.S. Pat. No. 5,117,389 by Tom D.H. Yiu. Also, for an example high-density ROM memory cell fabricating technology, see U.S. Pat. No. 4,974,042 by Ashida et al.
Conventional fabrication of a flat-cell ROM involves exposing the surface of a silicon substrate between N.sup.+ buried layers or between an N.sup.+ buried layer and a P-well while patterning a gate. The exposed substrate surface may be overetched due to a process margin in etching back a gate spacer for formation of an LDD (Lightly Doped Drain) structure in a peripheral region. Hence, junctions, such as an N/P junction, in completed transistors are destroyed and pitted, resulting in a decrease in the breakdown voltage of the transistors. Furthermore, a reduced design rule leads to the decrease of a channel width to the width of a gate electrode in a cell transistor and of a cell current, thereby impeding low voltage operation.
In many cases of the related art, a source/drain of a transistor in a peripheral region is formed by ion implantation in self alignment with a gate or a spacer, making it difficult to employ a butted contact as a word line contact due to an exposed P-well or substrate. That is, when a contact hole for a butted contact is formed to cross over a gate poly and part of the exposed substrate, the gate is connected to the source/drain by a metal filled in the contact hole. Therefore, the butted contact is not available. To form a desirable word line contact through an interlayer insulating layer on a gate poly in a structure other than the above butted contact, process margin should be ensured against misalignment and variation in the critical dimension of skew. Thus, the word line being the gate poly is formed to be wider than a contact hole in order to account for the process margin. This increased word line width increases chip area and impedes realization of high integration.
As described above, the conventional flat-cell ROM cannot operate at low voltage and high speed if a cell transistor has a low cell current due to junction destruction and reduced breakdown voltage. Another problem is that since a butted contact cannot be used as a contact for supplying a voltage to a word line, a contact margin should be ensured, resulting in a wider word line and, thus, an increased chip area.